Constructing a low power multiplier using Modified Booth Encoding Algorithm in redundant binary number system

This paper introducing a novel technique called as redundant binary booth algorithm. The redundant binary in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. Generally, in a high radix modified Booth encoding algorithm the partial products are reduced in multiplication process. But it yields complexity in producing in generation of hard multiples. Therefore booth encoding scheme along with redundant binary scheme solve this problem by using Booth encoder, RB partial product generator, RB partial product accumulator, RB to NB converter stages. In this process after booth encoding the two booths encoded digits are polarized in to differential pair to restore the effective RB partial product reduction rate without the NB to RB conversion over head. A new Booth encoding algorithm is presented in this project to simplify the generation of hard multiples and reduce the number of RB partial products without introducing any form of correction vector. The proposed algorithm binds two adjacent Booth encoders to compose an RB partial product by exploiting the RB coding. The common bit of the two adjacent Booth encoders is used as an enabler for the polarization of two equally weighted partial product bits. As the formation of an RB partial product digit is analogous to the charge sharing of two oppositely charged atoms in a covalent bond, we name the algorithm the covalent redundant binary Booth encoding. IndexTerms—Arithmetic circuit, Booth encoding algorithm, digital multiplier, energy-delay product, redundant binary adder (RBA).